DocumentCode :
2867141
Title :
Towards a New Nanoelectronic Cosmology
Author :
Hartmann, Joël
Author_Institution :
STMicroelectronics, Crolles
fYear :
2007
fDate :
11-15 Feb. 2007
Firstpage :
31
Lastpage :
37
Abstract :
Gone forever, are the days of smooth roadmap scaling, with its more-or-less-simple design rules, adequate supply voltages, and unimpeded circuit shrinkage. As scaling moved ahead to nanometer dimensions, things changed. Devices became more difficult to predict, and global performance degraded due to leakage and dispersion. One of the consequences of this deteriorating situation has been that increased parameter variability has led to a significant mismatch between simulation and actual-measurement results, at all levels. While many of these effects have been already well-known to analog designers, the surprise, now, is that they are more broadly important, even in digital design, where previously available noise margins have almost disappeared. Clearly, deep understanding and modeling of all underlying physical causes is urgently required to guide the right choices at all levels. Conceptually, such understanding will lead to acceptable levels of performance, manufacturability, and yield, at ever-decreasing feature sizes. Meanwhile, the increased parameter variability observed today, as one technology node invites the next, reveals the tight coupling of the four seemingly- independent dimensions of design, motivating the need to configure a new nano-cosmology, one in which global optimization results only from an intricate balance between the process, device, circuit, and system aspects of design. In this new nano-cosmology, the emerging concept of generalized design-for-manufacturability (GDfM) unifies current design-for-manufacturability (DfM), manufacturing-for-design (MfD), and design-for-yield (DfY), coupling all of the above-mentioned dimensions within a new space where their inter-dependence is revealed and exploited. Tightly-coupled physical-electrical-mechanical-process modeling and simulation, will allow early detection of the impact of design choices at all levels. This creates a 4D knowledge continuum reminiscent of the ideas of general relativity, ones e- xtremely rich in consequences for the future of nanoelectronic design.
Keywords :
design for manufacture; nanoelectronics; 4D knowledge continuum; circuit shrinkage; design for manufacturability; design for yield; manufacturing for design; nanoelectronic cosmology; nanoelectronic design; noise margins; parameter variability; Batteries; CMOS process; CMOS technology; Circuits; Degradation; Germanium silicon alloys; Silicon germanium; Temperature; Threshold voltage; Tunneling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
ISSN :
0193-6530
Print_ISBN :
1-4244-0853-9
Electronic_ISBN :
0193-6530
Type :
conf
DOI :
10.1109/ISSCC.2007.373575
Filename :
4242252
Link To Document :
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