• DocumentCode
    2867267
  • Title

    Monolithic multiplier/divider

  • Author

    Schmoock, J.

  • Author_Institution
    Raytheon Co., Mountain View, CA, USA
  • Volume
    XXII
  • fYear
    1979
  • fDate
    14-16 Feb. 1979
  • Firstpage
    230
  • Lastpage
    231
  • Abstract
    A monolithic analog multiplier/divider circuit which achieves less than 0.03% FS nonlinearity error with a large signal bandwidth of 3MHz will be reported. Design also incorporates nonlinearity compensation.
  • Keywords
    Bandwidth; Bipolar transistors; Circuit synthesis; Costs; Differential amplifiers; Fabrication; Geometry; Nonlinear equations; Resistors; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1979 IEEE International
  • Conference_Location
    Philadelphia, PA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1979.1155930
  • Filename
    1155930
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2867267