A tolerance analysis for manufacturing to direct process capability improvement efforts

A tolerance analysis for manufacturing which can be used to direct process capability improvement efforts is presented. This approach is a direct application of Taguchi´s Quality Engineering by Design (QED) techniques, and incorporates both process simulation and product manufacturing data. The resulting combination provides a useful weapon against variation to process and device engineers in a manufacturing environment. The focus is on determining an appropriate process variation reduction strategy in order to achieve device performance specifications. An illustrative case study is presented on the variation reduction of the nMOS threshold voltage (Vtn) in the RIT CMOS process. A tolerance reduction model is developed which determines where variation reduction efforts will be most rewarded. Based on this model, a practical tolerance reduction strategy is established