Title :
Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections
Author :
Deng, Jie ; Patil, Nishant ; Ryu, Koungmin ; Badmaev, Alexander ; Zhou, Chongwu ; Mitra, Subhasish ; Wong, H. S Philip
Author_Institution :
Stanford Univ., CA
Abstract :
1D carbon nanotube FET (CNFET)-based circuits offer 4.6times faster FO4 speed and 12times energy-delay product improvement over 32nm node Si CMOS (including diameter and doping variations), provided circuits can be built that are immune to misaligned and metallic nanotubes. A design technique that guarantees correct logic operation in the presence of misaligned nanotubes is also presented.
Keywords :
carbon nanotubes; field effect transistor circuits; network synthesis; carbon nanotube transistor circuits; circuit-level performance benchmarking; energy-delay product improvement; misaligned nanotubes; CMOS process; Capacitance; Carbon nanotubes; Circuit synthesis; Delay; Doping; Inverters; Logic circuits; Logic functions; Testing;
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0853-9
Electronic_ISBN :
0193-6530
DOI :
10.1109/ISSCC.2007.373592
