• DocumentCode
    2867388
  • Title

    Nanotopography effects on chemical mechanical polishing for shallow trench isolation

  • Author

    Lee, Brian ; Gan, Terence ; Boning, Duane ; Hester, Pat ; Poduj, Noel ; Baylies, Winthrop

  • Author_Institution
    MIT, Cambridge, MA, USA
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    425
  • Lastpage
    432
  • Abstract
    Nanotopography is the nanometer-scale height variation that occurs over lateral millimeter length scales on unpatterned silicon wafers. This height variation can result in excess thinning of surface films during chemical mechanical polishing (CMP) of shallow trench isolation (STI) structures. The development of an accurate nanotopography CMP modeling and characterization procedure will allow for the proper diagnosis of potential problems due to wafer nanotopography in a given STI CMP process. In this work, a nanotopography modeling methodology is proposed which relates the length scale of nanotopography features to the length scale of the CMP process. A combined density/step-height polishing model indicates that when the nanotopography features occur over a range comparable to or shorter than the planarization length, appreciable thinning is predicted. A contact wear CMP model similarly shows that as the pad stiffness increases, film thinning also increases. These simulation results indicate that the effect of nanotopography on STI CMP may be a substantial concern
  • Keywords
    chemical mechanical polishing; elemental semiconductors; isolation technology; semiconductor process modelling; silicon; surface topography; Si; chemical mechanical polishing; contact wear; film thinning; nanotopography; pad stiffness; planarization; shallow trench isolation; silicon wafer; simulation model; step height; surface topography; Chemicals; Fabrication; Gallium nitride; Lithography; Nanotopography; Planarization; Semiconductor device modeling; Semiconductor films; Silicon; Surface topography;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Advanced Semiconductor Manufacturing Conference and Workshop, 2000 IEEE/SEMI
  • Conference_Location
    Boston, MA
  • ISSN
    1078-8743
  • Print_ISBN
    0-7803-5921-6
  • Type

    conf

  • DOI
    10.1109/ASMC.2000.902623
  • Filename
    902623