Title :
Testing a high density logic masterslice
Author_Institution :
IBM Corp., Hopwell Junction, NY, USA
Abstract :
Testing strategy for high density logic in a manufacturing environment will be covered. The approach is applicable to all wiring personalities of a T2L gate logic masterslice.
Keywords :
Circuit faults; Circuit testing; Driver circuits; Integrated circuit testing; Latches; Logic design; Logic testing; Sequential analysis; Test pattern generators; Wiring;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1979 IEEE International
Conference_Location :
Philadelphia, PA, USA
DOI :
10.1109/ISSCC.1979.1155940
