DocumentCode
2867495
Title
A monolithic, charge-balancing successive-approximation A/D technique
Author
Redfern, T. ; Connolly, James ; Sing Chin ; Frederiksen, T.
Author_Institution
National Semiconductor Corp., Santa Clara, CA, USA
Volume
XXII
fYear
1979
fDate
14-16 Feb. 1979
Firstpage
176
Lastpage
177
Abstract
A modified 
(potentiometric) A/D approach which reduces die area (fewer resistors are required), inherently allows a bipolar input with a single polarity reference, and permits linearity adjustment at wafer sort via a laser programmed ROM, will be presented.
(potentiometric) A/D approach which reduces die area (fewer resistors are required), inherently allows a bipolar input with a single polarity reference, and permits linearity adjustment at wafer sort via a laser programmed ROM, will be presented.Keywords
Capacitors; Charge transfer; Circuits; Decoding; Dynamic range; Dynamic voltage scaling; Logic design; Matrix converters; Pulse inverters; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1979 IEEE International
Conference_Location
Philadelphia, PA, USA
Type
conf
DOI
10.1109/ISSCC.1979.1155944
Filename
1155944
Link To Document