An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS

Author

Vangal, Sriram ; Howard, Jason ; Ruhl, Gregory ; Dighe, Saurabh ; Wilson, H. ; Tschanz, James ; Finan, David ; Iyer, Priya ; Singh, Arvind ; Jacob, Tiju ; Jain, Shailendra ; Venkataraman, Sriram ; Hoskote, Yatin ; Borkar, Nitin

Author_Institution

Intel, Hillsboro, OR

fYear

2007

fDate

11-15 Feb. 2007

Firstpage

98

Lastpage

589

Abstract

A 275mm² network-on-chip architecture contains 80 tiles arranged as a 10 times 8 2D array of floating-point cores and packet-switched routers, operating at 4GHz. The 15-F04 design employs mesochronous clocking, fine-grained clock gating, dynamic sleep transistors, and body-bias techniques. The 65nm 100M transistor die is designed to achieve a peak performance of 1.0TFLOPS at 1V while dissipating 98W.

Keywords

CMOS integrated circuits; floating point arithmetic; integrated circuit design; logic design; microprocessor chips; network-on-chip; 1 V; 1.28TFLOPS network-on-chip; 100M transistor die; 15-F04 design; 4 GHz; 65 nm; 98 W; CMOS integrated circuits; body-bias techniques; dynamic sleep transistors; fine-grained clock gating; floating-point cores; mesochronous clocking; packet-switched routers; Circuits; Clocks; Frequency; Jacobian matrices; Microprocessors; Network-on-a-chip; Sleep; Tellurium; Tiles; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

1-4244-0853-9

Electronic_ISBN

0193-6530

Type

conf

DOI

10.1109/ISSCC.2007.373606

Filename

4242283