Cascadability and in-situ learning for VLSI multi-layer networks

Progress in analogue VLSI technology for neural networks has been steady rather than spectacular, but there now exists a number of well-proven designs which have been used to build small-scale demonstrators. There are at least two outstanding issues, however, which need to be addressed before real-world applications, such as intelligent sensors or autonomous robots, become possible: cascadability, to ensure that networks of arbitrary size and complexity can be assembled, and on-chip learning, so that the hardware is capable of adapting to changing environments or to the availability of new data. This paper focuses on both of these issues