A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption

Author

Yoshida, Yutaka ; Kamei, Tatsuya ; Hayase, Kiyoshi ; Shibahara, Shinichi ; Nishii, Osamu ; Hattori, Toshihiro ; Hasegawa, Atsushi ; Takada, Masashi ; Irie, Naohiko ; Uchiyama, Kunio ; Odaka, Toshihiko ; Takada, Kiwamu ; Kimura, Keiji ; Kasahara, Hironori

Author_Institution

Renesas Technol., Tokyo

fYear

2007

fDate

11-15 Feb. 2007

Firstpage

100

Lastpage

590

Abstract

A 4320MIPS four-core SoC that supports both SMP and AMP for embedded applications is designed in 90nm CMOS. Each processor-core can be operated with a different frequency dynamically including clock stop, while keeping data cache coherency, to maintain maximum processing performance and to reduce average operating power. The 97.6mm² die achieves a floating-point performance of 16.8GFLOPS

Keywords

CMOS digital integrated circuits; cache storage; integrated circuit design; logic design; low-power electronics; microprocessor chips; system-on-chip; 4320MIPS four-processor core SMP/AMP; 90 nm; CMOS integrated circuits; clock frequency; clock stop; data cache coherency; embedded applications; low power consumption; system-on-chip; Clocks; Energy consumption; Energy management; Finishing; Frequency conversion; Frequency estimation; Hardware; Read-write memory; System buses; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

1-4244-0853-9

Electronic_ISBN

0193-6530

Type

conf

DOI

10.1109/ISSCC.2007.373607

Filename

4242284