Title :
A 25W SoC with Dual 2GHz Power Cores and Integrated Memory and I/O Subsystems
Author :
Zongjian Chen ; Ananthanarayanan, Parameswaran ; Biswas, Santosh ; Campbell, Bradford ; Hao Chen ; Desai, Shaishav ; Go, David ; Goel, Rohit ; von Kaenel, V. ; Kassoff, J. ; Klass, F. ; Weichun Ku ; Li, Tong ; Lin, James ; Malik, Krystyna ; Mehta, A. ; Mu
Author_Institution :
PA Semi, Santa Clara, CA
Abstract :
An SoC is presented with dual 2GHz Powertrade cores, coherent crossbar interconnect, 2MB L2 cache, and memory and I/O subsystem. The chip consumes a maximum of 25W of power. The 115mm2 die is implemented in a 65nm 8M process with low-power design techniques. Circuits to improve system performance under power constraints are discussed
Keywords :
cache storage; integrated circuit design; integrated memory circuits; logic design; low-power electronics; system-on-chip; 2 GHz; 2 MBytes; 25 W; 65 nm; I/O subsystems; L2 cache; coherent crossbar interconnect; dual Power cores; integrated memory subsystems; low-power design techniques; system-on-chip; Circuits; Clocks; Delay; Frequency; Phase detection; Random access memory; Table lookup; Temperature; Voltage; Writing;
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0853-9
Electronic_ISBN :
0193-6530
DOI :
10.1109/ISSCC.2007.373609
