Title :
The Implementation of the 65nm Dual-Core 64b Merom Processor
Author :
Sakran, Nabeel ; Yuffe, Marcelo ; Mehalel, Moty ; Doweck, Jack ; Knoll, Ernest ; Kovacs, Avi
Author_Institution :
Intel, Haifa
Abstract :
Merom is a dual-core 64b processor implementing the Coretrade architecture. The 143mm2 die has 291M transistors in a 65nm 8M process. The shared 4MB 16-way L2 cache uses PMOS power gating to minimize leakage. The processor operates in a wide core frequency range of 1 to 3GHz, a bus frequency range of 666 to 1333MHz and voltage range of 0.85 to 1.325V, while providing 40% better power performance.
Keywords :
cache storage; integrated circuit design; logic design; microprocessor chips; 0.85 to 1.325 V; 1 to 3 GHz; 16-way L2 cache; 4 MBytes; 64 bit; 65 nm; 666 to 1333 MHz; Core architecture; PMOS power gating; dual-core Merom processor; Assembly; Clocks; Error correction; Frequency; Power supplies; Redundancy; Testing; Thermal management; Thermal sensors; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0853-9
Electronic_ISBN :
0193-6530
DOI :
10.1109/ISSCC.2007.373610
