Passives partitioning for single package single chip SoC on 32nm RFCMOS technology

Using a multilayer organic package substrate, we demonstrate that future system-on-chip with co-existing digital and radio integrated circuits can be partitioned to have critical RF inductors/transformers on package and active devices and capacitors on silicon, which enables cost and form factor reduction as well as design of radios on low resistivity substrate. As proof of concept, we present an example of silicon/package co-design, where a WLAN bandpass filter has been designed using 3D inductors on-package and multi-finger-capacitors on a 32nm silicon process. The design is validated both experimentally and through full wave electromagnetic simulation.