Optimization on Layout Style of Diode Stackup for On-Chip ESD Protection

Author

Chun-Yu Lin ; Mei-Lian Fan

Author_Institution

Dept. of Appl. Electron. Technol., Nat. Taiwan Normal Univ., Taipei, Taiwan

Volume

14

Issue

2

fYear

2014

fDate

Jun-14

Firstpage

775

Lastpage

777

Abstract

The diode stackup has been used as on-chip electrostatic discharge (ESD) protection for some applications in which the input/output signal swing is higher than V_DD or lower than V_SS. A novel ESD protection structure of diode stackup is proposed for effective on-chip ESD protection. Experimental results in 65-nm CMOS process show that the optimization on layout style can improve the ESD robustness, decrease the turn-on resistance, and lessen the parasitic capacitance of the diode stackup.

Keywords

CMOS integrated circuits; electrostatic discharge; integrated circuit layout; optimisation; semiconductor diodes; CMOS process; diode stackup; input signal swing; layout style optimization; on-chip ESD protection; on-chip electrostatic discharge protection; output signal swing; parasitic capacitance; size 65 nm; turn-on resistance; Electrostatic discharges; Layout; Resistance; Robustness; Semiconductor diodes; System-on-chip; Thyristors; Diode; electrostatic discharge (ESD); layout; stackup;

fLanguage

English

Journal_Title

Device and Materials Reliability, IEEE Transactions on

Publisher

ieee

ISSN

1530-4388

Type

jour

DOI

10.1109/TDMR.2014.2311130

Filename

6763105