A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500 MHz-to-8 GHz) All-Static CMOS AD PLL in 65nm SOI

Author

Rylyakov, A.V. ; Tierno, J.A. ; English, G.J. ; Friedman, D. ; Meghelli, M.

Author_Institution

IBM T.J. Watson, Yorktown Heights, NY

fYear

2007

fDate

11-15 Feb. 2007

Firstpage

172

Lastpage

173

Abstract

An all-static CMOS 65nm SOI ADPLL has a fully programmable loop filter and a 3^rd-order DeltaSigmamodulator. The DCO is a 3-stage, static-inverter-based ring-oscillator programmable in 768 frequency steps. The ADPLL locks from 500MHz to 8GHz at 1.3V 25degC, and 90MHz to 1.2GHz at 0.5V 100degC. The area is 200times150mum ² and it dissipates 8mW/GHz at 1.2V and 1.6mW/GHz at 0.5V. The synthesized 4GHz clock has period jitter of 0.7ps_rms, and long-term jitter of 6ps_rms. The phase noise is -110dBc/Hz at 10MHz offset

Keywords

CMOS digital integrated circuits; delta-sigma modulation; digital phase locked loops; logic gates; oscillators; silicon-on-insulator; 0.09 to 8 GHz; 0.5 to 1.3 V; 100 C; 20 C; SOI; all-static CMOS ADPLL; delta-sigma modulator; phased lock loop; static-inverter-based ring-oscillator; wide power-supply range PLL; wide tuning-range PLL; Circuit testing; Clocks; Digital circuits; Filters; Inverters; Jitter; Latches; Phase detection; Phase frequency detector; Phase locked loops;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

1-4244-0853-9

Electronic_ISBN

0193-6530

Type

conf

DOI

10.1109/ISSCC.2007.373349

Filename

4242320