A code transition delay model for ADC test

We propose a new fault model for static linearity testing of analog-to-digital converters (ADCs). Faults in the analog sub-circuit (ASC) manifest as a delay or advance of the code transition points, when the triangle wave input is applied. The delays or advances are measured in terms of the number of clocks that occur between the ideal case transition and the actual transition between two given codes. These differences are calculated for both the lower edge and the upper edge of a given code and are then used to calculate the differential linearity error (DLE) at that code. This technique considers time ordering of the codes which the histogram method does not. It also requires less hardware and is more conducive to a built-in self-test (BIST) implementation because we use only 6 registers rather than a register for every code that the ADC produces. The technique is validated on several CMOS flash ADCs