Modeling chaos in on-chip ultra-wideband chaotic oscillator

An ultra-wideband on-chip chaotic oscillator is demonstrated. This consists of a chaotic oscillator and a source follower buffer. Time evolution of output signal is highly aperiodic and frequency spectrum is widespread from DC to 300MHz. To model an inherent chaos in the circuit, CMOS inverter coupled with an electrostatic discharge protection circuit, gate-ground nMOS and gate source pMOS, is designed and fabricated. In the numerical model, three nonlinearities such as electrostatic discharge equivalent capacitance, high dynamic short current in the inverter, and transmission equivalent inductance are included. The results show that coupling between ESD current and supply current, and ESD rectification are the main causes to bring chaos in this structure.