Title :
A 40GHz DLL-Based Clock Generator in 90nm CMOS Technology
Author :
Chuang, Chi-Nan ; Liu, Shen-luan
Author_Institution :
Nat. Taiwan Univ., Taipei
Abstract :
A 2-to-5GHz multi-phase multi-period-locked DLL is fabricated in a 90nm CMOS technology. At 5GHz, the measured rms jitter is 0.874ps and the peak-to-peak jitter is 7.56ps. The multi-phase DLL is used for a 40GHz clock generator. The core area is 0.374times0.326mm2 and the power consumption is 45mW at 1V.
Keywords :
CMOS digital integrated circuits; clocks; delay lock loops; 1 V; 2 to 5 GHz; 40 GHz; 45 mW; 90 nm; CMOS technology; DLL-based clock generator; multi-phase multi-period-locked DLL; CMOS technology; Character generation; Charge pumps; Circuits; Clocks; Delay; Frequency measurement; Phase detection; Semiconductor device measurement; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0853-9
Electronic_ISBN :
0193-6530
DOI :
10.1109/ISSCC.2007.373352
