• DocumentCode
    2868186
  • Title

    A fault-tolerant 64K dynamic RAM

  • Author

    Cenker, R. ; Clemons, D. ; Huber, Werner ; Petrizzi, J. ; Procyk, F. ; Trout, G.

  • Author_Institution
    Bell Laboratories, Allentown, PA, USA
  • Volume
    XXII
  • fYear
    1979
  • fDate
    14-16 Feb. 1979
  • Firstpage
    150
  • Lastpage
    151
  • Abstract
    A 64K MOS RAM, featuring 100ns worst-case column access time, 128 refresh cycles, and pin compatibility with 16K RAMs, will be described. Polysilicon bit lines provide a high cell/column capacitance ratio, while spare memory elements improve yield.
  • Keywords
    Buffer storage; Capacitance; DRAM chips; Decoding; Electronics packaging; Fault tolerance; Impedance; Read-write memory; Solid state circuit design; Solid state circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1979 IEEE International
  • Conference_Location
    Philadelphia, PA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1979.1155986
  • Filename
    1155986
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2868186