A high-performance single-phase Phase-Locked-Loop with fast line-voltage amplitude tracking

This paper presents a single-phase Phase-Locked-Loop (PLL) system to reject the impact of input voltage amplitude variation. The proposed PLL is based on the unbalanced DQ transformation which doesn´t require the generation of orthogonal. Aside from the input phaseangle tracking feedback loop, another peak-voltage detection loop is enclosed to fast track the input signal amplitude, thereby reducing the output second-order harmonic frequency ripple by as much as 80% in most cases. The proposed PLL also allows for the rejection of the dc offset of the input signal, which is thus deemed advantageous due to the ease of implementation, ideal zero steady-state error output, and the offset rejection. Analytical simulation and experimental results are presented for verification purposes.