• DocumentCode
    2868224
  • Title

    A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC

  • Author

    Shin, Dongsuk ; Song, Janghoon ; Chae, Hyunsoo ; Kim, Kwan-Weon ; Choi, Young Jung ; Kim, Chulwoo

  • Author_Institution
    Korea Univ., Seoul
  • fYear
    2007
  • fDate
    11-15 Feb. 2007
  • Firstpage
    184
  • Lastpage
    595
  • Abstract
    An ADDLL is designed to achieve low jitter, fast lock time and nearly 50% duty cycle with an open-loop duty-cycle corrector. The ADDLL operates over a frequency range from 440MHz to 1.5GHz with 15 cycles of maximum lock-in time and occupies 0.053mm2 in 0.18mum 1.8V CMOS. The peak-to-peak jitter is 7ps at 1.5GHz and the power consumption is 43mW.
  • Keywords
    delay lock loops; jitter; 0.18 micron; 1.8 V; 43 mW; 440E3 to 1.5 GHz; all-digital DCC; fast-lock ADDLL; open-loop duty-cycle corrector; Clocks; Delay lines; Detectors; Error correction; Frequency synchronization; Jitter; Open loop systems; Phase detection; Signal generators; Signal resolution;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    1-4244-0853-9
  • Electronic_ISBN
    0193-6530
  • Type

    conf

  • DOI
    10.1109/ISSCC.2007.373355
  • Filename
    4242326
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2868224