• DocumentCode
    2868562
  • Title

    A 72mW 0.03mm2 Inductorless 40Gb/s CDR in 65nm SOI CMOS

  • Author

    Toifl, Thomas ; Menolfi, Christian ; Buchmann, Peter ; Hagleitner, Christoph ; Kossel, Marcel ; Morf, Thomas ; Weiss, Jonas ; Schmatz, Martin

  • Author_Institution
    IBM, Rueschlikon
  • fYear
    2007
  • fDate
    11-15 Feb. 2007
  • Firstpage
    226
  • Lastpage
    598
  • Abstract
    A quarter-rate CDR circuit is based on a dual-loop approach where sampling phases are generated by a phase-programmable PLL that is controlled by a digital DLL. Implemented in 65nm SOI CMOS, the chip occupies 0.03mm2 and consumes 1.8mW/Gb/s. Measurements confirm 40Gb/s operation with a BER <10-12 at a maximum frequency-offset of 400ppm. The phase relation between data and edge samples can be programmed within plusmn0.1 UI.
  • Keywords
    CMOS integrated circuits; clocks; silicon-on-insulator; synchronisation; 65 nm; 72 mW; SOI CMOS; digital DLL; inductorless CDR; phase-programmable PLL; quarter-rate CDR circuit; Circuits; Clocks; Delay; Detectors; Filters; Phase detection; Phase locked loops; Phased arrays; Sampling methods; Voltage-controlled oscillators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    1-4244-0853-9
  • Electronic_ISBN
    0193-6530
  • Type

    conf

  • DOI
    10.1109/ISSCC.2007.373376
  • Filename
    4242347
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2868562