Fast extraction of high-frequency parallel admittance of Through-Silicon-Vias and their capacitive coupling-noise to active regions

We introduce an accurate and efficient method to extract high-frequency parallel admittance (capacitance and conductance) among multiple Through-Silicon-Vias (TSVs). Our method utilize the analytical expression of TSV´s MOS capacitance and the 3D quasi-electrostatic (QES) scalar potential Green´s function in layered media for extracting the inverse of complex capacitance matrix of TSV segments, with consideration of low conductivity silicon bulk region and high conductivity well regions with VDD/VSS contact rails. The elements of the complex capacitance matrix of TSV segments can be summed up to the final results of parallel admittance matrix of TSVs. Our method is verified against a full-wave Finite-Element-Method (FEM) electromagnetic solver HFSS, and shows more than 103X speed-up with good accuracy in the frequency range from digital circuit clock frequency to 100 GHz (<7% error for the self-admittance, the dominant quantity, and <13% error for the mutual-admittance, the smaller quantity). The complex capacitance matrix of TSV segments and the scalar potential Green´s function is also used to extract the noise coupling coefficient from TSV to active regions, which is also verified by HFSS simulation.