A 6-bit segmented RZ DAC architecture with up to 50-GHz sampling clock and 4 Vpp differential swing

A novel, distributed, return-to-zero (RZ) power digital-to-analog converter (DAC) architecture is presented. The circuit features 14 independent data bits - 7 for the 3 most significant bits (MSB) and 7 for the 3 least significant bits (LSB) - each running at up to 50 Gb/s. It is fabricated in a production 130-nm SiGe BiCMOS technology and operates as a large swing arbitrary waveform generator suitable for a variety of wireline, fiber optic, and instrumentation applications. The measured small signal differential gain and bandwidth of the clock path are 19 dB and 43 GHz, respectively. An output swing of 2 Vpp per side is observed. Spectral measurements demonstrate multi-bit modulation at carrier frequencies as high as 50 GHz. To the best of our knowledge, this marks the highest clock frequency, highest voltage swing 6-bit DAC.