Integrated crosstalk and oxide integrity analysis in DSM designs

Author

Arviad, N.V. ; Suresh, P.R. ; Sivakumar, V. ; Pal, Chandrani ; Das, Debaprasad

Author_Institution

Texas Instrum. India Ltd., Bangalore, India

fYear

2001

fDate

2001

Firstpage

518

Lastpage

523

Abstract

The deep sub micron era has brought numerous signal integrity and reliability issues to the forefront. The analysis of signal integrity and reliability problems increases the design cycle time. In this paper we present a common framework to analyze two important DSM issues, crosstalk glitch and gate oxide integrity. We describe many important features of the flow such as timing based pruning, glitch propagation, overshoot and undershoot glitch analysis techniques. Finally, we also present the crosstalk analysis results on some of the ASIC designs

Keywords

VLSI; application specific integrated circuits; crosstalk; integrated circuit design; integrated circuit interconnections; integrated circuit reliability; timing; ASIC designs; DSM designs; crosstalk glitch; deep sub micron era; design cycle time; glitch propagation; overshoot glitch analysis; oxide integrity analysis; reliability issues; signal integrity; timing based pruning; undershoot glitch analysis; Capacitance; Crosstalk; Degradation; Lead compounds; Logic; Power supplies; Signal design; Timing; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 2001. Fourteenth International Conference on

Conference_Location

Bangalore

ISSN

1063-9667

Print_ISBN

0-7695-0831-6

Type

conf

DOI

10.1109/ICVD.2001.902710

Filename

902710