DocumentCode
2868801
Title
A 1.5V 200MS/s 13b 25mW DAC with Randomized Nested Background Calibration in 0.13μm CMOS
Author
Clara, Martin ; Klatzer, Wolfgang ; Seger, Berthold ; Giandomenico, Antonio Di ; Gori, Luca
Author_Institution
Infineon Technol., Villach
fYear
2007
fDate
11-15 Feb. 2007
Firstpage
250
Lastpage
600
Abstract
Time-domain randomization of the unit current-cell refresh period converts the tonal behavior of cyclic background calibration into noise. Together with nested calibration of all DAC-segments a low-frequency SFDR of 83.7dB is achieved. The chip is fabricated in a standard 0.13mum CMOS process. Clocked at 200MHz, it consumes 25mW from a 1.5V supply.
Keywords
CMOS integrated circuits; calibration; digital-analogue conversion; 0.13 micron; 1.5 V; 13 bit; 200 MHz; 25 mW; CMOS process; DAC; cyclic background calibration; randomized nested background calibration; time-domain randomization; tonal behavior; CMOS technology; Calibration; Clocks; Energy consumption; Frequency; Noise shaping; Solid state circuits; Time domain analysis; Voltage; Wideband;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
1-4244-0853-9
Electronic_ISBN
0193-6530
Type
conf
DOI
10.1109/ISSCC.2007.373388
Filename
4242359
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