RTL-based Clock Recovery Architecture with All-Digital Duty-Cycle Correction

Author

Wang, Ping-Ying ; Yang, Meng-Ta ; Chen, Shang-Ping ; Lin, Meng-Hsueh ; Yang, Jing-Bing

Author_Institution

MediaTeK, Hsinchu

fYear

2007

fDate

11-15 Feb. 2007

Firstpage

254

Lastpage

600

Abstract

RTL-based clock-recovery (CR) loop offers jitter filtering and frequency multiplication with a data-rate range from 76 to 496Mb/s. The design has direct digital phase shift capability with 20ps resolution for generating write-pulse recording sequences and digital duty-cycle correction for generating 50% duty-cycle clocks. The CR loop occupies 0.08mm² in 0.13mum CMOS and consumes 12mW with 1.2V supply at a channel rate of 496Mb/s.

Keywords

CMOS digital integrated circuits; clocks; digital phase locked loops; frequency multipliers; jitter; synchronisation; 0.13 micron; 1.2 V; 12 mW; 20 ps; 76 to 496 Mbit/s; CMOS; RTL-based clock recovery; all-digital duty-cycle correction; direct digital phase shift capability; frequency multiplication; jitter filtering; write-pulse recording sequences; Calibration; Circuit noise; Clocks; Delay lines; Frequency; Hardware design languages; Phase locked loops; Power supplies; Signal generators; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

1-4244-0853-9

Electronic_ISBN

0193-6530

Type

conf

DOI

10.1109/ISSCC.2007.373390

Filename

4242361