Title :
A 1.9Gb/s 358mW 16-to-256 State Reconfigurable Viterbi Accelerator in 90nm CMOS
Author :
Anders, Mark ; Mathew, Sanu ; Hsu, Steven ; Krishnamurthy, Ram ; Borkar, Shekhar
Author_Institution :
Intel, Hillsboro, OR
Abstract :
A 16-to-256 state coarse-grain reconfigurable Viterbi accelerator fabricated in 1.3V, 90nm dual-Vt CMOS technology is described for 3.8GHz operation, with 1.9Gb/s data rate in 32-state mode. Radix-4 ripple-carry ACS circuits, reconfigurable path metric read/write control and tree-bitline traceback memory circuits with programmable ring-buffer decoders enable 358mW total power, measured at 1.3V, 50 degC, with performance scalable to 2.35Gb/s at 17V, 50 degC.
Keywords :
CMOS integrated circuits; Viterbi decoding; carry logic; coprocessors; microwave integrated circuits; 1.3 V; 1.9 Gbit/s; 17 V; 2.35 Gbit/s; 3.8 GHz; 358 mW; 50 C; 90 nm; dual-threshold voltage CMOS technology; programmable ring-buffer decoders; radix-4 ripple-carry ACS circuits; reconfigurable Viterbi accelerator; reconfigurable path metric read/write control; tree-bitline traceback memory circuits; CMOS process; CMOS technology; Counting circuits; Decoding; Flexible printed circuits; Polynomials; Power generation; Power measurement; Read-write memory; Viterbi algorithm;
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0853-9
Electronic_ISBN :
0193-6530
DOI :
10.1109/ISSCC.2007.373391
