DocumentCode :
2868895
Title :
A 50mW HSDPA Baseband Receiver ASIC with Multimode Digital Front-End
Author :
Martelli, Chiara ; Reutemann, Robert ; Benkeser, Christian ; Huang, Qiuting
Author_Institution :
Swiss Fed. Inst. of Technol., Zurich
fYear :
2007
fDate :
11-15 Feb. 2007
Firstpage :
260
Lastpage :
601
Abstract :
A multimode digital front-end for EDGE, WCDMA, and WLAN modes and a WCDMA/HSDPA receiver is implemented in 0.13mum 1P6M CMOS technology occupying 5.15mm2 and dissipating 0.8/48/31 mW in EDGE/HSDPA/WLAN modes, respectively.
Keywords :
3G mobile communication; CMOS digital integrated circuits; UHF integrated circuits; application specific integrated circuits; code division multiple access; radio receivers; wireless LAN; 0.13 micron; 0.8 mW; 1P6M CMOS technology; 31 mW; 48 mW; EDGE; HSDPA baseband receiver ASIC; WCDMA; WLAN; multimode digital front-end; Application specific integrated circuits; Baseband; Clocks; Decoding; Fading; Finite impulse response filter; Frequency synchronization; Multiaccess communication; Multipath channels; RAKE receivers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
ISSN :
0193-6530
Print_ISBN :
1-4244-0853-9
Electronic_ISBN :
0193-6530
Type :
conf
DOI :
10.1109/ISSCC.2007.373393
Filename :
4242364
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2868895
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