A new architecture for frequency-selective digital predistortion linearization for RF power amplifiers

This paper presents a new architecture for frequency-selective digital predistortion (DPD) for two-band PA linearization. The algorithm used accounts for differential memory effects up to 5th order for bands which can be arbitrarily spaced. The preliminary demonstration study is performed using 2-band multi-tone signals with various tone spacing and band separation. The test signal and the linearization algorithm were implemented on a field programmable gate array (FPGA). The linearization algorithm was applied to an RF amplifier at 965 MHz. In the preliminary test for the multitone signals, the 3rd and 5th order distortion were reduced below the noise floor yielding an IMD/ACPR of 55 dB.