Scheduling Instructions for Soft Errors in Register Files

Subsequently to the wall of performance and power consumption, the dependability of computing, caused by soft errors, has become a growing design concern. Since Register Files (RFs) are very frequently accessed and available protecting techniques usually provoke significant power penalty and performance degradation, soft errors occurred in RFs are among the top reasons for affecting system reliability. Based on our previous analytical method, which is able to estimate the living probability of target registers, we propose a compiler optimization approach that can enhance the reliability of programs without extra costs. Under the constraints of instruction dependencies, we describe the concrete algorithm for basic block scheduling in a dynamic programming fashion, whose basic idea is to decrease the total live intervals that are vulnerable to soft errors during the execution process. We also present a register renaming method for improving the capability of scheduling. Experimental results from the MiBench benchmarks indicate that the average reliability of programs have been improved for 4.41% without palpable overhead.