Title :
DC error reduction in bipolar opamps
Author_Institution :
Consultant, Jalisco, Mexico
Abstract :
A bipolar opamp design providing 100μV offset voltage, 1μV/°C drift and 20pA bias current will be described. In contrast to FETs, performance is maintained to 125°C.
Keywords :
Bipolar transistors; Capacitance; Clamps; FETs; Integrated circuit noise; Leakage current; Low voltage; Low-frequency noise; Semiconductor device noise; Temperature;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1980 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1980.1156040
