DocumentCode
2869174
Title
DC error reduction in bipolar opamps
Author
Widlar, R.
Author_Institution
Consultant, Jalisco, Mexico
Volume
XXIII
fYear
1980
fDate
13-15 Feb. 1980
Firstpage
204
Lastpage
205
Abstract
A bipolar opamp design providing 100μV offset voltage, 1μV/°C drift and 20pA bias current will be described. In contrast to FETs, performance is maintained to 125°C.
Keywords
Bipolar transistors; Capacitance; Clamps; FETs; Integrated circuit noise; Leakage current; Low voltage; Low-frequency noise; Semiconductor device noise; Temperature;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1980 IEEE International
Conference_Location
San Francisco, CA, USA
Type
conf
DOI
10.1109/ISSCC.1980.1156040
Filename
1156040
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