Title :
Comparison of Split-Versus Connected-Core Supplies in the POWER6 Microprocessor
Author :
James, Norman ; Restle, Phillip ; Friedrich, Joshua ; Huott, Bill ; McCredie, Bradley
Author_Institution :
IBM, Austin, TX
Abstract :
The POWER6trade is a dual-core microprocessor fabricated in a 65nm SOI process with 10 levels of low-k copper interconnects. Chips with split- and connected-core power supplies are fabricated, modeled, and tested, showing both the advantages and disadvantages of each. On-chip noise measurements are compared to simulation. The noise measurements and simulation both show that the shorted core power grid design has less noise and a higher maximum frequency.
Keywords :
microprocessor chips; power supply circuits; silicon-on-insulator; 65 nm; POWER6 microprocessor; connected core power supplies; dual-core microprocessor; low-k copper interconnects; on chip noise measurements; power grid design; shorted core power grid design; silicon-on-insulator; split core power supplies; Clocks; Delay; Latches; Microprocessors; Noise figure; Noise measurement; Power grids; Power supplies; Storms; Timing;
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0853-9
Electronic_ISBN :
0193-6530
DOI :
10.1109/ISSCC.2007.373412
