Title :
A 40-to-800MHz Locking Multi-Phase DLL
Author :
Kim, Young-Sang ; Park, Seung-Jin ; Kim, Yong-Sub ; Jang, Dong-Bi ; Jeong, Seh-Woong ; Park, Hong-June ; Sim, Jae-Yoon
Author_Institution :
Pohang Univ. of Sci. & Technol.
Abstract :
A delay matrix and a gradual switching of shunt capacitors in delay cells are proposed for a wide-range-locking multi-phase DLL. With an interpolating resistor network, delay step error is greatly reduced by error averaging. The DLL, implemented in 0.13mum CMOS, has a locking range of 40 to 800MHz. With 40 phases, the maximum delay step error is 16.7ps at 700MHz. The chip dissipates 43mW at 700MHz from a 1.2V supply and the measured jitter is 12pspp and 1.6psrms.
Keywords :
CMOS integrated circuits; capacitors; delay lock loops; 0.13 micron; 1.2 V; 40 to 800 MHz; 43 mW; CMOS technology; delay lock loops; delay matrix; delay step error; interpolating resistor network; shunt capacitors; Circuits; Delay; Frequency; Industrial electronics; Optical network units; Optical pumping; Pulse width modulation inverters; Resistors; Switches; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0853-9
Electronic_ISBN :
0193-6530
DOI :
10.1109/ISSCC.2007.373416
