Implementation of the CELL Broadband Engine in a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V

Author

Pille, J. ; Adams, C. ; Christensen, T. ; Cottier, S. ; Ehrenreich, S. ; Kono, F. ; Nelson, D. ; Takahashi, O. ; Tokito, S. ; Torreiter, O. ; Wagner, O. ; Wendel, D.

Author_Institution

IBM, Boeblingen

fYear

2007

fDate

11-15 Feb. 2007

Firstpage

322

Lastpage

606

Abstract

The 65nm CELL Broadband Enginetrade design features a dual power supply, which enhances SRAM stability and performance using an elevated array-specific power supply, while reducing the logic power consumption. Hardware measurements demonstrate low-voltage operation and reduced scatter of the minimum operating voltage. The chip operates at 6GHz at 1.3V and is fabricated in a 65nm CMOS SOI technology.

Keywords

CMOS digital integrated circuits; SRAM chips; low-power electronics; microprocessor chips; silicon-on-insulator; 1.3 V; 6 GHz; 65 nm; CELL Broadband Engine; SOI technology; array-specific power supply; dual-supply SRAM arrays; logic power consumption reduction; low-voltage operation; CMOS logic circuits; CMOS technology; Energy consumption; Engines; Hardware; Logic arrays; Logic design; Power supplies; Random access memory; Stability;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

1-4244-0853-9

Electronic_ISBN

0193-6530

Type

conf

DOI

10.1109/ISSCC.2007.373424

Filename

4242395