Author :
Wang, Y. ; Ahn, H. ; Bhattacharya, U. ; Coan, T. ; Hamzaoglu, F. ; Hafez, W. ; Jan, C.-H. ; Kolar, P. ; Kulkarni, S. ; Lin, J. ; Ng, Y. ; Post, I. ; Wei, L. ; Zhang, Y. ; Zhang, K. ; Bohr, M.
Abstract :
A low-power high-speed SRAM macro is implemented in an ultra-low-power 8M 65nm CMOS for mobile applications. The 1Mb macro features a 0.667μm2 low-leakage memory cell and operates with supply voltage from 0.5V to 1.2V. It operates at a frequency of 1.1 GHz at 1.2V and 250MHz at 0.7V. Leakage is reduced to 12μA/Mb at the data retention voltage of 0.5V. The measured bitcell leakage from the SRAM array is ~2pA/b at retention voltage with integrated leakage reduction schemes.
Keywords :
CMOS memory circuits; SRAM chips; mobile computing; 0.5 to 1.2 V; 1.1 GHz; 250 MHz; 65 nm; 8M CMOS; SRAM design; integrated leakage reduction; low-leakage memory cell; mobile application; CMOS technology; Circuits; Dynamic voltage scaling; Energy consumption; Frequency; Leakage current; MOS devices; Random access memory; Subthreshold current; Voltage control;
