Title :
A 65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy
Author :
Verma, Naveen ; Chandrakasan, Anantha P.
Author_Institution :
Massachusetts Inst. of Technol., Cambridge, MA
Abstract :
A 65nm 256kb 8T SRAM operates in sub-V, at 350mV. Peripheral assists eliminate sub-V, bitline leakage without limiting read current, and for a given area, sense-amplifier redundancy reduces read errors from offsets by a factor of five compared with device upsizing.
Keywords :
CMOS memory circuits; SRAM chips; amplifiers; low-power electronics; 350 mV; 65 nm; 8T SRAM; bitline leakage elimination; peripheral assists; sense-amplifier redundancy; CMOS logic circuits; Charge pumps; Degradation; Error probability; Logic circuits; MOS devices; Random access memory; Redundancy; Space technology; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0853-9
Electronic_ISBN :
0193-6530
DOI :
10.1109/ISSCC.2007.373427
