DocumentCode
2869454
Title
A Sub-200mV 6T SRAM in 0.13μm CMOS
Author
Zhai, Bo ; Blaauw, David ; Sylvester, Dennis ; Hanson, Scott
Author_Institution
Michigan Univ., Ann Arbor, MI
fYear
2007
fDate
11-15 Feb. 2007
Firstpage
332
Lastpage
606
Abstract
A deep-subthreshold 6T SRAM functions from 1.2V to 193mV and is fabricated in an industrial 0.13μm CMOS technology. It provides greater than 2× energy-efficiency improvement over the previously proposed MUX-based subthreshold SRAM designs while using half the area. Adjustable footer and headers are introduced, as well as body-bias techniques to allow low-voltage operation.
Keywords
CMOS memory circuits; SRAM chips; low-power electronics; 0.13 micron; 1.2 to 0.193 V; 6T SRAM; CMOS technology; adjustable footer; adjustable header; body-bias techniques; low-voltage operation; subthreshold SRAM; Circuit stability; Environmental management; Frequency; Inverters; MOS devices; Pulse generation; Random access memory; Robustness; Threshold voltage; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
1-4244-0852-0
Electronic_ISBN
0193-6530
Type
conf
DOI
10.1109/ISSCC.2007.373429
Filename
4242400
Link To Document