• DocumentCode
    2869609
  • Title

    A 14mW Fractional-N PLL Modulator with an Enhanced Digital Phase Detector and Frequency Switching Scheme

  • Author

    Ferriss, Mark ; Flynn, Michael P.

  • Author_Institution
    Michigan Univ., Ann Arbor, MI
  • fYear
    2007
  • fDate
    11-15 Feb. 2007
  • Firstpage
    352
  • Lastpage
    608
  • Abstract
    A 2.2GHz fractional-N synthesizer with a digital phase detector and a dual switching scheme is presented. An additional feedback loop incorporating phase oversampling helps to achieve a measured noise performance of -133dBc (-106dBc) at a 10MHz (1 MHz) offset. The MSK modulation rate is 927.5kb/s. The 0.7mm2 prototype IC, implemented in a 0.13mum CMOS process, consumes 14mW from a 1.4V supply.
  • Keywords
    CMOS integrated circuits; delta-sigma modulation; phase locked loops; 0.13 micron; 1.4 V; 14 mW; 2.2 GHz; CMOS process; digital phase detector; dual switching scheme; fractional-N PLL modulator; frequency-switching scheme; phase oversampling; Digital modulation; Feedback loop; Integrated circuit noise; Noise measurement; Phase detection; Phase frequency detector; Phase locked loops; Phase measurement; Phase modulation; Synthesizers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    1-4244-0853-9
  • Electronic_ISBN
    0193-6530
  • Type

    conf

  • DOI
    10.1109/ISSCC.2007.373439
  • Filename
    4242410
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2869609