• DocumentCode
    2869707
  • Title

    A dense gate matrix layout style for MOS LSI

  • Author

    Lopez, A. ; Hung-Fai Law

  • Author_Institution
    Bell Laboratories, Murray Hill, NJ, USA
  • Volume
    XXIII
  • fYear
    1980
  • fDate
    13-15 Feb. 1980
  • Firstpage
    212
  • Lastpage
    213
  • Abstract
    This paper will discuss a layout style - gate matrix - for CMOS VLSI in the polysilicon gate technology. Approach, simplifying and unifying layout procedure by using an orderly structure, a matrix, characterized by rows of polysilicon and columns of diffusion, has been tested in a 20,000- transistor layout.
  • Keywords
    CMOS logic circuits; CMOS technology; Design automation; Large scale integration; Logic design; Logic devices; MOS devices; Microprocessors; Silicon; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1980 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1980.1156074
  • Filename
    1156074
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2869707