Title :
A dense gate matrix layout style for MOS LSI
Author :
Lopez, A. ; Hung-Fai Law
Author_Institution :
Bell Laboratories, Murray Hill, NJ, USA
Abstract :
This paper will discuss a layout style - gate matrix - for CMOS VLSI in the polysilicon gate technology. Approach, simplifying and unifying layout procedure by using an orderly structure, a matrix, characterized by rows of polysilicon and columns of diffusion, has been tested in a 20,000- transistor layout.
Keywords :
CMOS logic circuits; CMOS technology; Design automation; Large scale integration; Logic design; Logic devices; MOS devices; Microprocessors; Silicon; Very large scale integration;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1980 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1980.1156074
