Title :
A 1.6pJ/bit 96% Stable Chip-ID Generating Circuit using Process Variations
Author :
Su, Y. ; Holleman, J. ; Otis, B.
Author_Institution :
Washington Univ., Seattle, WA
Abstract :
A 128b 6.3pJ/b, 96%-stable chip-ID generation circuit using process variation is designed in a 0.13mum CMOS technology. The circuit consumes 162nW from a 1V supply at low readout frequencies and 6.34muW at 1 Mb/s. Two layout techniques are designed and fabricated to provide a performance comparison of power consumption and ID reliability
Keywords :
CMOS integrated circuits; identification technology; integrated circuit design; integrated circuit reliability; 0.13 micron; 1 Mbit/s; 1 V; 128 bit; 162 nW; 6.34 muW; CMOS technology; ID reliability; chip-ID generation circuit; power consumption; process variations; Circuits; Clocks; Decoding; Energy consumption; Hamming distance; Latches; Packaging; Power dissipation; Random access memory; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0853-9
Electronic_ISBN :
0193-6530
DOI :
10.1109/ISSCC.2007.373466
