DocumentCode
2870139
Title
A 0.28pJ/b 2Gb/s/ch Transceiver in 90nm CMOS for 10mm On-Chip interconnects
Author
Mensink, Eisse ; Schinkel, Daniel ; Klumperink, E. ; van Tuijl, E. ; Nauta, Bram
Author_Institution
Twente Univ., Enschede
fYear
2007
fDate
11-15 Feb. 2007
Firstpage
414
Lastpage
612
Abstract
A low-swing transceiver for 10mm-long 0.54mum-wide on-chip interconnects is presented. A capacitive pre-emphasis transmitter lowers the power and increases the bandwidth. The receiver uses DFE with a power-efficient continuous-time feedback filter. The transceiver, fabricated in 1.2V 90nm CMOS, achieves 2Gb/s. It consumes 0.28pJ/b, which is 7times lower than earlier work
Keywords
CMOS integrated circuits; continuous time filters; decision feedback equalisers; integrated circuit interconnections; low-power electronics; transceivers; 0.54 micron; 1.2 V; 10 mm; 2 Gbits/s; 90 nm; CMOS; DFE; capacitive preemphasis transmitter; continuous-time feedback filter; low-swing transceiver; on-chip interconnects; Bandwidth; Capacitance; Clocks; Decision feedback equalizers; Energy consumption; Filters; Integrated circuit interconnections; Transceivers; Transmitters; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
1-4244-0853-9
Electronic_ISBN
0193-6530
Type
conf
DOI
10.1109/ISSCC.2007.373470
Filename
4242441
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