Title :
Heterodyne Phase Locking: A Technique for High-Frequency Division
Author_Institution :
California Univ., Los Angeles, CA
Abstract :
The use of multiple downconversion mixers in a PLL can provide frequency division with arbitrary integer or fractional divide ratios. A heterodyne PLL, realized in a 0.13mum CMOS process, achieves a lock range of 64GHz to 70GHz with no external tuning. The circuit consumes 6mW from a 1.2V supply
Keywords :
CMOS integrated circuits; frequency dividers; millimetre wave integrated circuits; millimetre wave mixers; phase locked loops; 0.13 micron; 1.2 V; 6 mW; 64 to 70 GHz; CMOS process; PLL; downconversion mixers; frequency division; heterodyne phase locking; high-frequency division; CMOS technology; Capacitance; Circuits; Frequency conversion; Phase locked loops; Phase noise; Radio frequency; Topology; Tuning; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0853-9
Electronic_ISBN :
0193-6530
DOI :
10.1109/ISSCC.2007.373477
