Author :
Pashley, R. ; Terman, L.
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
The industry is continuing to shrink devices and increase integration levels. The panel will discuss the fundamental limits and practical barriers to the on-going development of VLSI, including reliability and yield effects of scaling, hot electron trapping, soft errors, current density limitations, leakage and circuit design tradeoffs. The focus will be on technology, device and circuit considerations.
Keywords :
CMOS technology; Capacitance; Delay; Dry etching; Electric resistance; Isolation technology; Laboratories; Lithography; MOS devices; Very large scale integration;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1980 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1980.1156106
