A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications

Author

Palmer, R. ; Poulton, J. ; Dally, W.J. ; Eyles, J. ; Fuller, A.M. ; Greer, T. ; Horowitz, M. ; Kellam, M. ; Quan, F. ; Zarkeshvari, F.

Author_Institution

Rambus, Chapel Hill, NC

fYear

2007

fDate

11-15 Feb. 2007

Firstpage

440

Lastpage

614

Abstract

A power-efficient 6.25Gb/s transceiver in 90nm CMOS for chip-to-chip communication is presented, it dissipates 2.2mW/Gb/s operating at a BER of <10^-15 over a channel with -15dB attenuation at 3.125GHz. A shared LC-PLL, resonant clock distribution, a low-swing voltage-mode transmitter, a low-power phase rotator, and a software-based CDR and an adaptive equalizer are used to reduce power

Keywords

CMOS integrated circuits; adaptive equalisers; clocks; low-power electronics; phase locked loops; transceivers; 14 mW; 3.125 GHz; 6.25 Gbit/s; 90 nm; CMOS integrated circuits; adaptive equalizer; low-power phase rotator; low-swing voltage-mode transmitter; phase locked loop; resonant clock distribution; serial chip-to-chip communication; shared LC-PLL; software-based CDR; transceiver; Capacitors; Clocks; Frequency; Phase detection; Phase locked loops; Regulators; Testing; Transceivers; Transmitters; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

1-4244-0853-9

Electronic_ISBN

0193-6530

Type

conf

DOI

10.1109/ISSCC.2007.373483

Filename

4242454