DocumentCode :
2870371
Title :
A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer
Author :
Hidaka, Y. ; Weixin Gai ; Hattori, Akira ; Horie, Toshihiro ; Jiang, Jian ; Kanda, Kouichi ; Koyanagi, Yoshio ; Matsubara, Satoshi ; Osone, H.
Author_Institution :
Fujitsu Labs. of America, Sunnyvale, CA
fYear :
2007
fDate :
11-15 Feb. 2007
Firstpage :
442
Lastpage :
443
Abstract :
Fabricated in 90nm CMOS, the chip consumes 545mW and has a pattern-balancing adaptive equalizer that is stable for any data patterns including those with a strong peak component at a single frequency. The adaptive equalizer yields a gain at fs/2 relative to fs/16 varying from -1.7 to 2.2dB for any 8B10B encoded Ethernet frames filled with a fixed data byte
Keywords :
CMOS integrated circuits; adaptive equalisers; transceivers; -1.7 to 2.2 dB; 10.3 Gbit/s; 3.1 Gbit/s; 4-channel transceiver macro; 545 mW; 90 nm; CMOS integrated circuit; data patterns; pattern-balancing adaptive equalizer; pattern-tolerant adaptive equalizer; Adaptive control; Adaptive equalizers; Automatic control; Bandwidth; Dielectric losses; Intersymbol interference; Laboratories; Optical receivers; Programmable control; Transceivers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
ISSN :
0193-6530
Print_ISBN :
1-4244-0853-9
Electronic_ISBN :
0193-6530
Type :
conf
DOI :
10.1109/ISSCC.2007.373484
Filename :
4242455
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2870371
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