Aladdin: a high performance, distributed memory multiprocessor

Describes the design of the Aladdin architecture and the implementation of the prototype which Alliant Techsystems is under contract to deliver to DARPA and the Army´s CCNVEO. The primary goal of the Aladdin project is to design an architecture that has high throughput and is compact, programmable, modular, reconfigurable and scalable. The architecture must be suitable for automatic target recognition (ATR) and radar processing, get flexible enough to be reconfigured for applications such as avionics processing. The architecture is demonstrated in a soupcan-sized prototype that consists of 64 320C30´s with 92 MBytes of memory, and 16 Alliant Techsystems proprietary Parallel Recirculating Pipeline (PREP) chips supported by 512 KBytes of multiport memory. It has a throughput of 2 GFLOPS, 1 GOPS, 1056 MIPS, and can be programmed in Ada, C and Image Algebra