• DocumentCode
    2870444
  • Title

    A 0.8V 10b 8OMS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing

  • Author

    Yoshioka, Masato ; Kudo, Masahiro ; Mori, Toshihiko ; Tsukamoto, Sanroku

  • Author_Institution
    Fujitsu Labs., Kawasaki
  • fYear
    2007
  • fDate
    11-15 Feb. 2007
  • Firstpage
    452
  • Lastpage
    614
  • Abstract
    A low-voltage design is developed for amplifiers in the pipelined ADC, regulating overdrive voltage to be constant over PVT variations. A prototype 10b 80MS/S pipelined ADC is fabricated in a 90nm CMOS process. The ADC consumes 6.5mW from a 0.8V supply and occupies 1.18 times 0.54mm2
  • Keywords
    CMOS integrated circuits; amplifiers; analogue-digital conversion; low-power electronics; 0.8 V; 10 bit; 6.5 mW; 90 nm; CMOS process; PVT variations; amplifiers; low-voltage design; pipelined analog-to-digital converter; regulated overdrive voltage biasing; Analog circuits; Bandwidth; Dynamic range; Energy consumption; Frequency; Low voltage; Noise level; Switched capacitor circuits; Switching circuits; Topology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    1-4244-0853-9
  • Electronic_ISBN
    0193-6530
  • Type

    conf

  • DOI
    10.1109/ISSCC.2007.373489
  • Filename
    4242460
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2870444