DocumentCode :
2870742
Title :
Performance limits of E/D NMOS VLSI
Author :
Ratnakumar, K. ; Meindl, J. ; Bartelink, D.
Author_Institution :
Stanford University, Stanford, CA, USA
Volume :
XXIII
fYear :
1980
fDate :
13-15 Feb. 1980
Firstpage :
72
Lastpage :
73
Abstract :
This report will discuss an analytic MOST model, including subthreshold and short-channel effects, which accurately describes measured MOST behavior for channel lengths down to 1μm and predicts fundamental limits ( 
m, 
V and 
fJ) for optimal E/D inverters.
m, V and fJ) for optimal E/D inverters.Keywords :
Avalanche breakdown; Breakdown voltage; Low voltage; MOS devices; MOSFETs; Poisson equations; Solid modeling; Solid state circuits; Threshold voltage; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1980 IEEE International
Conference_Location :
San Francisco, CA, USA
Type :
conf
DOI :
10.1109/ISSCC.1980.1156132
Filename :
1156132
Link To Document :
