Title :
A 1.2-to-8V Charge-Pump with Improved Power Efficiency for Non-Volatille Memories
Author :
Richelli, A. ; Mensi, L. ; Colalongo, L. ; Rolandi, P.L. ; Kovacs-Vajna, Zs M.
Author_Institution :
Brescia Univ.
Abstract :
A charge-pump architecture is presented with an improved power efficiency and a high voltage output compared to the known Dickson and Favrat architectures due to partial reuse of the charge stored on the capacitors. An 8-stage charge pump fabricated in a 0.13mum CMOS process has a 1.2V supply and a 100MHz clock. The measured performance indicates that the efficiency can be 25% higher than a Favrat cell. The efficiency increases with the number of stages, reaching 60% with 10 stages.
Keywords :
CMOS integrated circuits; random-access storage; voltage multipliers; 0.13 micron; 1.2 to 8 V; 100 MHz; CMOS process; Dickson architectures; Favrat architectures; Favrat cell; charge-pump; improved power efficiency; nonvolatile memories; CMOS technology; Capacitors; Charge pumps; Circuits; Clocks; Flash memory; Parasitic capacitance; Power supplies; Switches; Threshold voltage;
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0853-9
Electronic_ISBN :
0193-6530
DOI :
10.1109/ISSCC.2007.373524
